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<div class="title">AXI Muckbucket </div>  </div>
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<h1><a class="anchor" id="intro_sec"></a>
Introduction</h1>
<ul>
<li>This is an AXI testbench. It uses UVM so unfortunately iverilog isn't sufficient. (I hope this changes soon.)</li>
<li>- Dual-top testbench</li>
<li>- Slave responder, no BFM (currently)</li>
<li>- Supports AXI3 and AXI4</li>
<li>- Supports all AXI data widths (8,16,32,64,128,256,512 and 1024)</li>
<li>- Supports 32-bit and 64-bit address widths</li>
<li>- Supports full and partial transfers.</li>
<li>- Supports aligned and unaligned transfers.</li>
<li>- Supports Fixed, Incrementing and Wrapped transfers.</li>
<li>- Supports toggling *ready and *valid. Including AXI-incompatibly mode which randomly asserts and deasserts valid before ready asserts.</li>
<li>- Fixed burst_type must be aligned. Unaligned Fixed transfers are not supported.</li>
<li>- Testbench side is event driven. No #'delays, no , etc</li>
<li>- Emulator friendly (TB side is event driven. no  or # delays)</li>
<li>- Pipelined AXI driver</li>
<li>- back to back transfers with 0 in-between wait clocks.</li>
<li>- Polymorphic interface</li>
<li>- <a class="el" href="params__pkg_8sv.html">params_pkg.sv</a> contains all dut parameters</li>
<li>- A master driver - acts as an AXI master</li>
<li>- A slave driver - acts as an AXI slave</li>
<li>- Coverage collector</li>
<li>- Scoreboard (counts address packets and response packets)</li>
<li></li>
<li>Good whitepaper on slave sequences:</li>
<li><a href="http://www.verilab.com/files/reactive_slaves_presentation.pdf">http://www.verilab.com/files/reactive_slaves_presentation.pdf</a></li>
<li><a href="http://www.verilab.com/files/litterick_uvm_slaves2_paper.pdf">http://www.verilab.com/files/litterick_uvm_slaves2_paper.pdf</a></li>
<li></li>
<li>Parallel/pipelined driver:</li>
<li><a href="https://www.quora.com/What-is-the-best-way-to-model-an-out-of-order-transaction-driver-in-UVM">https://www.quora.com/What-is-the-best-way-to-model-an-out-of-order-transaction-driver-in-UVM</a></li>
<li></li>
<li>Monitors</li>
<li><a href="https://verificationacademy.com/verification-horizons/june-2013-volume-9-issue-2/Monitors-Monitors-Everywhere-Who-Is-Monitoring-the-Monitors">https://verificationacademy.com/verification-horizons/june-2013-volume-9-issue-2/Monitors-Monitors-Everywhere-Who-Is-Monitoring-the-Monitors</a></li>
<li></li>
<li>verification plan (put in seperate doc):</li>
<li>- For each supported data width:</li>
<li>- check all 3 burst_types(e_FIXED, e_INCR, e_WRAP)</li>
<li>- all possible burst_sizes (including invalid, make sure they fail)</li>
<li>- all possible lens (only have a couple coverbins though,or any cross will be too large.)</li>
<li>- min (1), max, everything in-between ?</li>
<li>- stable *ready</li>
<li>- toggling *ready</li>
<li>- stable *valid</li>
<li>- toggling *valid</li>
<li>- AXI-incompabible *valid toggling (valid deasserts before ready asserts)</li>
<li>- back-to-back bursts (aw,w,b,ar,r)</li>
<li>- one clock delay between bursts (aw,w,b,ar,r)</li>
<li>- serial mode (aw, then w, then b, repeat) (ar, then r, repeat)</li>
<li>- pipelined (multiple aw, then multiple w, then multiple b, repeat) (multiple ar,then multiple r,repeat)</li>
<li>*/ </li>
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